Michael Garner received his PhD in Materials Science & Engineering from
Stanford University in 1978. He then joined Sandia National Labs as a
Process Engineer & Product Engineer. In 1983, he joined Intel where he
has worked in the Technology and Manufacturing Group, where he has managed
process and device modeling in Technology CAD, was a Manager in Components
Research, Director of Fab Materials and Materials Technology Operation. In
Components Research, he managed the Advanced Process Department where his
group explored chilled CMOS, GaAs IC Technology, Silicon on Insulator
transistor technology, Optical Interconnects, Advanced Gate Dielectrics,
and identifying safe replacements for materials with EHS issues. From
1998 through 2004, he was Director of Materials Technology Operation.
Since 2004 he has also been the leader of the Emerging Research Materials
Work Group of the International Technology Roadmap for Semiconductors which
is identifying critical materials, synthesis, metrology, and modeling
requirements for emerging research devices through ~2020. Most recently,
he is the Program Manager of External Materials Research in the Technology
Strategy Organization.
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