Kazuo Yano received the B. S., M. S., and Ph. D degrees from Waseda University, Japan, in 1982, 1984, 1993, respectively.
He joined the Central Research Laboratory, Hitachi Ltd. in 1984 and
now is the Project Leader, Sensor Net Strategic Project and also the
Laboratory Manager, Human Intelligence Laboratory, Advanced Research
Laboratory. He has been interested in the limitations of Si LSIs and
breakthrough technologies. He studied MOS/bipolar devices for
low-temperature computers, CMOS/BiCMOS logic circuits, and
single-electron devices and system-LSI design methodology/CAD tools.
From 1991 to 1992 he was a Visiting Scientist at the Arizona State
University, working on single-electron transport physics with Professor
D. K. Ferry. He has conceived the complementary pass-transistor logic
(CPL), and has also done pioneering work on the synthesis of
pass-transistor logic circuits (LEAP) and world-first room-temperature
single-electron memories. He supervised research teams of Hitachi's
SuperH and H8 microprocessors, low-power design, DRAM and flash
memories, IP-based system-on-chip design, interface-definition language
CWL, flexible logic-optimization methodology and tools, design for test,
and flexible computing engine. Since April 2004, he is managing emerging
sensor network research team. He also supervises research teams of
advanced human-machine interaction, computer vision, and quantum
information technologies. He is a co-author of the book Silicon-Based
Heterojunction Devices (Maruzen, 1991) and The VLSI Handbook (CRC Press and IEEE Press, 2000).
He is a member of the IEEE, the Japan Society of Applied Physics, and
the IEICE of Japan. He received 1994 IEEE Paul Rappaport Award, 1996
IEEE Lewis Winner Award and 1998 IEEE Jack Raper Award. He was a
solid-state device subcommittee member of IEDM, panel committee member of Design Automation Conference.
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